采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件...

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

说明：  基于fpga的信号发生器，通过调整按键可以生成正弦波，方波，三角波，锯齿波(Sine wave, square wave, triangular wave, sawtooth wave)

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences

FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters

Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.

电梯的设计・用来控制6层的电梯设计原来・VHDL语言-Elevator designed to control the lift design 6 original VHDL language

自己写的扩展功能时钟，增加了年、月日计时，verilog代码，已在spatarn3实现。-Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must