俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料...

nios processor example 1

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!

Lift Controller in vhdl using process statement and state disgram

下采样与灰度

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

说明：  基于FPGA的串口发送和接收，使用的verlilog语言(Using Verilog serial port program, send and receive.)

说明：  verilog语言书写，单周期CPU源码(single period CPU)

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)

VERILOG五POSPHY LEVEL3电路描述，可综合,已经过检验.-Five POSPHY LEVEL3 Verilog circuit description can be integrated, has been tested.