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ABencode
FPGA实现增量式光栅尺正交脉冲解码,基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)
- 2020-11-21 20:59:36下载
- 积分:1
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clock
本程序实现数字钟系统,有整点报时功能,可显示切换年月日,定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
- 2015-04-19 22:07:02下载
- 积分:1
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switch--circuit
最近交互式电源技术,软交换、同步整流、频率固定(Alternating expressions Power technology recently、Softswitch, synchronous rectification, fixed frequency)
- 2013-11-25 15:56:17下载
- 积分:1
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这时manchesite编码,VERILOG语言,VHDL的找本站我发的帖子
这时manchesite编码,VERILOG语言,VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
- 2023-07-15 16:55:02下载
- 积分:1
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业界标准的Verilog语法格式
verilog标准语法,还有很多的样例参考,学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分:1
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verilog时钟分频器~ 50hmz波特率9600bps,使用~
verilog分频器~时钟为50hmz,波特率采用9600bps~-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分:1
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0001_EPM3064最小系统模块_带JTAG_LED_2mm插针
EMP3064的开发板板,原理图,verilog例子,板子说明,规格书,全套资料(EMP3064 development board, schematics, Verilog examples, board instructions, specifications, a full set of information)
- 2020-12-01 09:29:26下载
- 积分:1
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MUX
说明: 用CASE实现4选1数据选择器 很实用 运用VERILOG(Using CASE to achieve 4 election 1 Data Selector practical use Verilog)
- 2008-09-11 11:37:35下载
- 积分:1
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Clock_1602
基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)
- 2011-06-29 00:58:51下载
- 积分:1
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看了好多网了,发现有2to4译码,3to8译码,今天我要用4to16译码,写完了就发了上来...
看了好多网了,发现有2to4译码,3to8译码,今天我要用4to16译码,写完了就发了上来-saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks
- 2022-03-09 18:15:27下载
- 积分:1