buffer for in/out data.

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

带load、clr等功能的寄存器-belt load, the function clr Register

verilog基础练习，介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation

REEDSOLOMON source code

this program does something im not sure what but all i want is to get into the damn site thank you

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom

鼎lpc1788尚开发板的vga的显示，1024x768(lpc1788board,lcd to vga display,1024x768)

说明：  有关risc-v cpu的问题,里面有一些有关cpu的设计(The problem of risc-v can be solved)

LCD例程 altera官方Verilog代码 详尽简单实用-LCD routines altera official Verilog code is simple and practical details

USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)