buffer for in/out data.

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

一种基于FPGA 实现DDDR SDRAM的控制器 (DDDR SDRAM controller based on FPGA)

RobustVerilog生成verilog工具(RobustVerilog version)

自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)

该计数器可以实现从0到1000的技术，程序简练执行效率高(counter1000)

LOW pass FIR filter for multirate processing

自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!

单片机与ＦＰＧＡ的通信　 功能 :单片机控制写FPGA一字节数据 单片机控制写FPGA一字节数据时钟 (注意读写数据端口可复用,也可分用) 单片机控制发送数据端口 -MCU and FPGA communication functions: SCM control FPGA to write a byte of data SCM control FPGA to write a byte of data clock (Note that the read and write data ports can be re-used, but also can be divided into use) SCM control to send data port

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)