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chuankou
本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1
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带load、clr等功能的寄存器
带load、clr等功能的寄存器-belt load, the function clr Register
- 2022-06-20 10:15:42下载
- 积分:1
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verilog基础练习,介绍怎样编写测试文件和仿真
verilog基础练习,介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation
- 2022-01-28 18:39:08下载
- 积分:1
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reed_solom
REEDSOLOMON source code
- 2010-04-30 17:44:52下载
- 积分:1
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Hamming_decoder-1
this program does something im not sure what but all i want is to get into the damn site thank you
- 2010-09-09 16:46:51下载
- 积分:1
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Tutorijal 6
说明: Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分:1
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LPC1788_VGA_COLOR
鼎lpc1788尚开发板的vga的显示,1024x768(lpc1788board,lcd to vga display,1024x768)
- 2014-12-15 13:34:06下载
- 积分:1
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riscv-invicta-master
说明: 有关risc-v cpu的问题,里面有一些有关cpu的设计(The problem of risc-v can be solved)
- 2020-07-01 23:00:02下载
- 积分:1
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LCD例程 altera官方Verilog代码 详尽简单实用
LCD例程 altera官方Verilog代码 详尽简单实用-LCD routines altera official Verilog code is simple and practical details
- 2022-09-20 01:40:03下载
- 积分:1
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USB2.0的IP核(详细verilog源码和文档)
USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
- 2020-12-24 18:49:04下载
- 积分:1