国外经典verilog代码，很适合初学者，其中的有些概念对老手也可以考虑下...

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

一种基于FPGA 实现DDDR SDRAM的控制器 (DDDR SDRAM controller based on FPGA)

1553B总线BC端的编程例子，做通了对于一个RT的测试。对于其他的RT测试和程序的例子原理相同。(The BC end of the 1553B bus programming examples)

异步复位状态机 -- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn -asynchronous reset state machine-- State Machine with Asynchronou "s Reset-- dowload from : www.fpga.com.cn

ip核的FFTverilog源代码，说明不是很具体-ip nuclear FFTverilog source code, that is not very specific

在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下 变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所 采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字 下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了 数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)

VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)

xilinx公司的virtex-5开发板原理图 需要的可以下载看一下 希望对你有帮助(xilinx company virtex-5 development board schematics can download look you want to help)

说明：  biss协议源码交流 verilog hdl源码，测试可用(Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.)

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