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VHDL与源代码包
VHDL与源代码包-and VHDL source code
- 2022-02-03 22:44:25下载
- 积分:1
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fft-matlab
FFT的MATLAB实现。非常完整的实现FFT过程,速度很快。(The FFT in MATLAB. Contains more than one source, the FFT process. Learning Reference essential)
- 2012-10-27 16:07:24下载
- 积分:1
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sdram_hr_hw_4port
这个是DE2上的SDRAM 四个端口的驱动代码,相当实用!(This is a four-port SDRAM on a DE2 driver code, very useful!)
- 2010-07-14 21:21:05下载
- 积分:1
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bhaswatiml
matlab code for communication
- 2013-11-07 00:43:24下载
- 积分:1
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Construction-and-Experimental-Evaluations-of-User
Construction and Experimental Evaluations of User-Centered Power
- 2011-11-29 08:35:34下载
- 积分:1
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VGA的实现
本代码是实现VGA的显示的,在quartus开发环境下能完整的实现VGA的彩色显示,彩色条纹,通过不同按键来实现不同的效果,对于初学者有很大的帮助。
- 2022-02-16 10:18:55下载
- 积分:1
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卡内基梅陇大学verilog课程讲义-unlocked
verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分:1
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8b10b Verilog
8bit/10bit编码Verilog实现(8bit/10bit Verilog Code)
- 2018-09-18 10:29:44下载
- 积分:1
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VHDL
先设计序列发生器产生序列:1011010001101010;再设计序列检测器,检测序列发生器产生序列,若检测到信号与预置待测信号相同,则输出“1”,否则输出“0”,并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分:1
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Xilinx_FPGA_FFT_Application_Note
Xilinx FPGA中FFT IP核的使用笔记,内部有FFT硬核的端口说明和具体设置以及源代码,对于数字信号处理研究人员,能图像处理、雷达成像、实时通信开发人员较多的开发时间!(Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port description and specific settings as well as the source code for digital signal processing, image processing, radar imaging, real-time communications developers more development time!)
- 2013-04-23 09:34:31下载
- 积分:1