VHDL实现简单的8位CPU doc文件上有源代码

实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl

说明：  文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)

DSP 程序的测试 很有用的 仪器上面用的-DSP testing procedures very useful in the above apparatus

verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)

VHDL book for reference

说明：  THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)

说明：  一个使用VHDL进行正弦波信号产生的历程，非常有用。(A sine wave signal generator using VHDL for the course, very useful.)

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)