VHDL实现简单的8位CPU doc文件上有源代码

黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)

电梯的vhdl设计，6层楼含开关门，警报，内部请求，外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests

Ethernet MAC-MII interface of Transmit

资源描述VGA视频图形阵列（VGA）接口是一三排15针de-15连接器。15针VGA接口是许多视频卡，发现电脑显示器，以及一些高清晰度电视机。在笔记本电脑或其他小型设备，迷你VGA端口有时用于全尺寸的VGA接口的地方。

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)

Conduct a digital system ( electronic lock ) using hierarchic methodology . An electronic lock is a device that allows access or opening of a system , as long as the key or combination to enter match with which it is predefined in said lock .

FFT with FIR created by students in univercity

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)