用 vhdl 语言实现的快速吠陀数学乘法

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

vhdl,七段数码管驱动程序，完成数字显示功能-vhdl, seven-segment digital tube driver, complete the digital display

说明：  使用Verilog，以Quartus II 为平台，编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)

本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.(This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.)

vhdl经典源代码――键盘接口设计，入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master

FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)

完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)

VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...

verilog alu 8bit for engineers

高级verilog编程实现讲义，全英文讲义 -Senior verilog programming lecture notes, handouts in English