用 vhdl 语言实现的快速吠陀数学乘法

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)

企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)

verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table

vhdl经典源代码――vga控制，入门者必须掌握-vhdl classical source code-- vga control, beginners must master

done pwm control using vhdl ,you can look at it.

IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)

说明：  使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)

AMBA总线的AHB+APB源程序，供初学者学习。(Verilog for AHB and APB)

基于FPGA 的12864液晶显示汉字，用verilog编写的。(12864 liquid crystal display Chinese characters based on FPGA, written in verilog.)