高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计...

说明：  一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

数字脉冲宽度调制，将输入的数字信号转换为对应占空比的模拟波形(Digital pulse width modulation, the digital signal is converted to the corresponding input of the duty cycle of the analog waveform)

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

该源码为VHDL语言编写的分频器，在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated

一个LED大屏幕接收卡的完整设计工程,有需要学习LED大屏幕控制的朋友可以参考

基于FPGA的fsk调制程序，包括载波的生成，nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)

一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter，explained about the realization of multi-channel and simulation )