万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！...

CPLD imlementation of I2C BUS Controller. The description has been made by VHDL

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。(QuartusII-based environment to create the form of modular composite video sync signal.)

本程序用于实现OFDM信道估计的LS算法的硬件仿真，基于FPGA开发的VHDL编写，给出了各模块的仿真波形图，供大家交流参考。

veirlog编写的PS2键盘通讯程序, 并有PS2接口的相关说明, Quartus II 8.1工程文件(veirlog written communication procedures PS2 keyboard, and a PS2 interface instructions, Quartus II 8.1 project file)

乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5

4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。(Xilinx ISE 12.3.nexy3.)

VHDL编写的4个led灯循环明暗变化，通过改变波形占空比实现，课堂作业自编程序-VHDL prepared by the four led lights cycle shading changes, by changing the waveform duty cycle to achieve, self-compiled class operating procedures

freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog