适用于FPGA的SOPC方面的元器件添加，如COMPNENT

一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)

vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange

offset_cancellation code for matlab to hdl

利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction

说明：  基于fpga的数字图像处理原理及应用源码(The principle and source code of digital image processing based on FPGA)

该代码为VHDL语言描述的AD579 SPI通讯程序，包括一些代码注解。(Thisis a SPI communication promgram of AD5791 designed with VHDL which compared with some discreption.)

使用FPGA控制永磁同步电机的代码，实现对永磁同步电机的控制功能。(Motor control by using FPGA)

高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard

control stepper motor by fpga card with vhdl program

the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit "s multiplication.