由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证...

FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错(FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA)

FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

说明：  FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)

基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)

对与单片机常用的功能看门狗，本程序用vhdl硬件语言实现次功能。-Commonly used with single-chip watchdog function, the procedures for using VHDL hardware language functions realize times.

用VHDL语言设计篮球24秒可控计时器功能说明：1.具有24秒计时、显示功能；              2.设置外部按键，完成清零、暂停、恢复控制；              3.24秒倒计时，时间间隔为1s；               4.时间到后发出报警信号，并在3s后解除。

verilogHDL语言编写，简单的FPGA脉冲程序，初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)

基于FPGA的键盘程序代码，可用单片机控制-FPGA-based keyboard program code can be used SCM control

说明：  这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.