跑马灯程序FPGA

IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)

四位加法器 数码管显示 组合电路 verilog(adder4 smg display combitional circuit verilog)

32-bit shifter, shifter, 32-bit.Very goog as a study file.

基于FPGA的PCI9054 LOCALBUS总线接口(PCI9054 interface program based on FPGA)

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months

DOCUMENT ON DISTRIBUTED ARITHMATIC

8位有符号编码的整数基改性

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)

4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中(4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device)

UML2 apprendre a modeliser a l aide de UML