一个以太网卡的硬件描述，可以参考进行设计网卡芯片。

使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,(the modulation of 16QAM based on FPGA)

运用Quartus在LCM中显示静态宫殿图形-Use Quartus in LCM display static graphics palace

这是我上大三时的电子设计题目，叫秒表的功能实现。利用ISE软件进行编程，代码是VHDL语言的，可以实现时（0-9）分（0-59）秒（0-59）即最大10小时的计数，对于不同开发板，可以适当修改代码，使之成为更加广泛的计数器。代码纯原创，请下载。

Qutuas II v7.1的key_gen 对sp1无效 这就是个v7.1 sp1的key_gen -Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

说明：  实现基于黑金开发板的实时时钟功能，显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)

8051core-Verilog FPGA的51单片机内核源代码! -8051core-Verilog FPGA 51 Singlechip kernel source code!

&单元格

红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)