一个以太网卡的硬件描述，可以参考进行设计网卡芯片。

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!

1、 利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、 利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、 输出波形要求： 在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz； 在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、 通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.

这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

ip核的FFTverilog源代码，说明不是很具体-ip nuclear FFTverilog source code, that is not very specific

说明：  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.

ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.

在BASYS3上实现跑马灯的功能。第一LED交替闪烁；第二LED由左至右逐个变亮，再逐个变暗；第三LED由右至左逐个变亮，再逐个变暗；第四LED由两边逐个变亮，再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)

说明：  一个红外遥控，可以学习其他的红外编码，并存储记忆，并且将学习到的编码发送(An infrared remote control)

用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)