LMS自适应均衡器

微波炉定时器集成电路的设计 1、 控制状态机：工作状态状态转换。 2、 数据装入电路：根据控制信号选择定时时间、测试数据或完成信号的装入。 3、 定时器电路：负责完成烹调过程中的时间递减计数和数据译码供给七段数码显示，同时还可以提供烹调完成时间的状态信号供控制状态机产生完成信号。 -microwave timer IC design a control state machine : state of the state conversion work. 2, data loading circuit : According to choose control signal timing, or the completion of the test data signal load. 3, timer circuit : responsible for the completion of the cooking process of counting and time decreasing supply data decoding digital paragraph 107, while cooking can also provide time to complete state control signal for the state machine generated signals.

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

文档主要是关于TFT-LCD的相关资料，是有关TFT-lcd芯片的结构与设计理念，对于在这方面学习的朋友有比较大帮助(402 output thinfilm transistorliqu idcrystal display(TFT-LCDdriver integrated circui(ICwith power controlbasedon the number of color stobe displaye disdescribed. Toachievethistypeofpowercontrol,referencevoltagebuffersare turnedonandoffaccordingtotheselectednumberofcolors.)

ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)

EDA技术与VHDL课件，利用EDA技术进行电子系统设计(EDA technology and VHDL courseware, the use of EDA technology for electronic system design)

verilog lcd2864 适合初学者(verilog lcd2864 )

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)

基于fpga的液晶驱动开发过程相关资料，用于借鉴和学习-Fpga-based LCD driver development process relevant information, for reference and learning