LMS自适应均衡器

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic

VHDL编程语言设计，显示灯，显示VHDL字样。-VHDL programming language design, indicator lights, indicating the word VHDL.

FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013

spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)

这是这本书的第四个版本，现在这个版本不仅提供了VHDL语言的覆盖面，但设计方法的信息，以及。此版本将指导读者通过创建一个VHDL设计的过程中，模拟设计，综合设计，放置和布线设计，使用的重要模拟验证的最终结果，新的技术，称为全速调试，提供了极其快速设计验证。在这个版本的设计，例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)

代码来源http://www.spacewire.co.uk/video.html，需要CRT显示ITU.656格式的视频的可以参考

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)

基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

Farrow 滤波器设计经典文章，作者是：FM.Gardner，farrow滤波器设计的始祖，经典值得推荐！（两篇文章）(Farrow filter design classic article, the author is: FM.Gardner, farrow filter design ancestor, classic worth recommending! (Two articles))