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hdb3_VHDL
hdb3 using language VHDL(Indoor using VHDL language)
- 2020-12-01 20:19:27下载
- 积分:1
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DSP-keshe
设计题目:基于MATLAB的FFT算法的设计
设计内容:
所设计的FFT算法应完成以下功能:
(1)在MATLAB环境下编写FFT算法(不调用系统现有函数);
(2)实现对选定图片进行FFT计算、还原(IFFT计算),并与系统FFT函数做对比,进行分析;
(3)设计GUI界面。
(Design topics: content based on the the MATLAB FFT algorithm design design: the design of the FFT algorithm should perform the following functions: (1) the FFT algorithm written in MATLAB environment (do not call existing function of the system) (2) to achieve the selected picture for FFT calculation, restore (IFFT calculation) system FFT function analysis (3) design GUI interface.)
- 2013-04-09 16:51:00下载
- 积分:1
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mul
实现有限域中乘法,输入二个普通二级制数,输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)
- 2014-01-12 22:52:38下载
- 积分:1
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基于sopc ep2c5开发板的液晶字符显示例程
基于sopc ep2c5开发板的液晶字符显示例程-Sopc ep2c5 development board based on liquid crystal character display routine
- 2022-05-24 11:31:06下载
- 积分:1
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RecentProjectCleaner
vs自定义插件开发,带卸载功能,经测试完全可用,分享给大家,可以学习!(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)
- 2014-12-24 11:35:54下载
- 积分:1
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这是一个verilog代码为根升余弦滤波器
this is a verilog code for root raised cosine filter
- 2022-05-25 01:29:30下载
- 积分:1
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这是使用VHDL语言编写的密码锁程序,供大家参考
这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference
- 2023-04-25 08:05:03下载
- 积分:1
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EDA
计数器的程序,eda编程用的,vhdl语言编程,大家下载看看吧(Program counter, eda programming used, vhdl programming
)
- 2010-12-22 20:47:02下载
- 积分:1
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mac_layer_switch_latest.tar
source code for Ethernet logic
- 2017-04-05 08:04:27下载
- 积分:1
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基于FPGA的OFDM信号传输系统VHDL源码
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
- 2022-02-13 14:58:13下载
- 积分:1