E VHDL数字电路设计

Spartan 3e - Active Power Meter-Spartan 3e- Active Power Meter

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)

针对FPGA一个实现vga显示的很好的例程，vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.

一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source

基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....

done pwm control using vhdl ,you can look at it.

Vhdl design z80 for altera users

Verilog 语言编写 PCI9054 控制器的接口电路，实现 PCI总线到本地 8 位总线的转接控制(The Verilog language writes the interface circuit of the PCI9054 controller to realize the transfer control of the PCI bus to the local 8 bit bus)

用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的-Using Verilog language organ procedures. GW48 teaching experiment with simulation boxes

说明：  对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)