基于FPGA的八位RISC CPU的设计

verilog file , FPGA controll vga display- verilog file , FPGA controll vga display

（1）用HDL设计一个多功能数字钟，包含以下主要功能：精确计时，时间可以24小时制或12小时制显示； （2）日历：显示年月日星期； （3）能用QuartusII软件仿真；

典型事例，从网上down的，希望对大家有用，-Typical examples, from the Internet down, and I hope useful for everyone,

ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。(ARM processor IP core, written in verilog processor and CPU architecture knowledge.)

1）选择一个语音信号作为分析对象，或录制一段语音信号； 2）对语音信号进行采样，画出采样前后语音信号的时域波形和频谱图； 3）利用MATLAB中的随机函数产生噪声加入到语音信号中，使语音信号被污染，然后进行频谱分析； 4）设计用于处理该语音信号的数字滤波器，给出滤波器的性能指标，画出滤波器的频率响应； 5）对被噪声污染的语音信号进行滤波，画出滤波前后信号的时域波形和频谱，并对滤波前后的信号进行比较和分析； 6）回放各步骤的语音信号，给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)

讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现-Explain the use of FPGA and other video processing chips of the circuit design and FPGA realization of the procedure

16次迭代的CORDIC算法，精度很高，可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)

基于FPGA的可控100进制可逆计数器，运行环境maxplus(Controlled 100 hex reversible counter FPGA-based operating environment maxplus)

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)