一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形...

CH2CH1VHDL 数字电路参考书所有程序3-CH2CH1VHDL digital circuit reference all three procedures

64点FFT代码 基4算法 Verilog(64-point FFT code radix-4 algorithm Verilog)

ＦＰＧＡ设计中的一些经典例子对学习ＦＰＧＡ的人会有帮助-FPGA design of some of the classic examples of people learning FPGA would be helpful

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

LDPC COded OFDM System

本文研究的IIC总线控制器具有如下特征 1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。 2.多主操作 3.软件可编程时钟频率 4.时钟拉伸和等待状态生成 5.软件可编程确认位 6.时钟同步设计 7.仲裁中断丢失，自动转移取消 8.开始/停止/重复启动检测/确认生成 9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection)

vga interface with text rom. font size 80x40. core need core regeneration.

SDRAM_DDR控制器verilog代码及中文说明文档。(The SDRAM_DDR controller Verilog code and documentation in chinese.)

说明：  canny 边缘检测基于梯度直方图的自适应阈值verilog实现(Canny edge detection based on gradient histogram adaptive threshold Verilog implementation)

音频spdif格式编解码，可以将音频格式在i2s dsd以及spdif之间转换(Spdif audio codec)