Spartan 3e

FPGA（赛灵思）试验箱 实验程序 有Audio,Buzzer,key,ledarray,ledseg.......(FPGA（赛灵思）试验箱 实验程序Audio,Buzzer,key,ledarray,ledseg)

浙江大学体系结构实验代码 实现流水线的forwarding(Architecture, Zhejiang University Experimental code pipeline forwarding)

4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.

说明：  基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

Xilinx的FPGA开发DEMO例程，功能相对来说比较全面，适合新手参考。-Xilinx FPGA development DEMO routines, function relatively comprehensive reference suitable for novice.

用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)

本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching

说明：  用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)

数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件-CNC dividing frequency of a project- including VHDL source code and compile the relevant documents after