Spartan 3e

龙芯CPU+IP+资源简介，希望大家能够了解自己开发的芯片。(Godson CPU+ IP+ Resource profile, hope that we can understand their own chips.)

vhdl参考程序，供初学者参考使用-VHDL reference procedures, their use and reference for beginners

wimax ofdm系统评估代码 wimax ofdm system code 很有参考价值(wimax ofdm system code)

VHDL 乘法器 源代码，很好的VHDL 入门学习例程序-Multiplier VHDL source code, a good learning example VHDL entry procedures

用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

说明：  使用Verilog HDL ，FM调制信号。(Using Verilog, HDL, and FM modulation signals.)

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)

fpga读取sd卡内容并且通过vga接口在显示器上显示图片(fpga read sd card contents and by vga interface to display pictures on the monitor)

主要通过频率分配 实现不同时间的变化 达到呼吸一闪一闪的效果