用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的

说明：  使用vivado和Xilinx开发板实现VGA图像显示，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)

RS(255,223)编码器程序 从一本书上看到的，很不错的(RS(255,223) encode , very good good good )

说明：  在FPGA板卡上面，通过单个按键实现串口的发送功能，带仿真需要自行修改一下工程配置(On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation)

LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)

电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)

tle转换为六根数的c++源代码，英文原版代码，测试可用(tle converted to six the number of c++ source code, the English original code, test available)

基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过-Stepper motor stepper motor position location system system block symbol file location stepper motor system Verilog HDL program design has been compiled through

异步复位状态机 -- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn -asynchronous reset state machine-- State Machine with Asynchronou "s Reset-- dowload from : www.fpga.com.cn

数字ic设计，二级缓存，格雷码，深度256，(Digital IC design, two level cache, gray code, depth 256.)