用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的

FPGA扫描LED显示灯，动态扫描,进行流水显示(FPGA Scan LED indicator lights, dynamic scanning, make the water show)

SRAM简单测试，测试其性能及其速度，判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)

that file is different I2S example

Vhdl实现的鼠标协议历程，代码可读性高，适合作为案例参考。-VHDL realize the course of the mouse protocol, code readable, suitable as a reference case.

在图像中

VHDL 波形防止抖动程序,学习试验材料(VHDL prevent jitter waveform procedures, the pilot study materials)

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.