Write their own extensions clock, an increase of the year, month day time, veril...

This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The fi rst program uses the programmed I/O approach and the second program uses interrupts.-This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The fi rst program uses the programmed I/O approach and the second program uses interrupts.

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)

我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application

dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL

8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages

基于CPLD的交通信号灯的实现，使用VHDL语言，使用不同颜色的二极管分别代表红黄绿三种信号灯。在数码管上可以分别显示倒计时。

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

A simple sequential lights