基于CPLD的交通信号灯的实现

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)

利用c控制adc，主要是控制字写入，状态控制。-C control the use of adc, is mainly controlled write, the state of control.

this program performs multiplexing and demultiplexing

网络通信中的MII接口 通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用 同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)

Comparator for Quartus

用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!

它是一个基于verilog的数字时钟，显示时-分-秒，它可以手动输入，并为时、分和秒分配3个开关第二，它数字时钟频率是实时设置的。我自己用逻辑开发的。。。

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL

Introduction to learn laboratry with altera quartus II 9.1

Fpga开发应用，jtag方面的源代码，VHDL-Fpga development and application, jtag in the source code, VHDL