我用过的verilog hdl写的SDRAM core源程序,经过测试应用

DDS的VHDL源代码，是数字QPSK调制解调中的重要组成部分。(DDS of the VHDL source code, the number of QPSK modulation and demodulation is an important part.)

spwm dcac逆变 fpga与单片机一起作用(sdad)

该模块实现一个寄存器堆的操作，其中前16个仅主机能写，规给为32-bit×32。后16个仅Micorblaze能写。读取没有限制。如果双方同时对同一地址进行读写操作，读回的数将是全1。(This module implement a register file of the operation, of which the first host 16 is only able to write rules to the 32-bit × 32. Micorblaze only 16 after the write. There is no limit to read. If the two sides at the same time to read and write operations to the same address, read back would have been a full one.)

vhdl经典源代码――ps2接口设计，入门者必须掌握-vhdl classical source code-- ps2 interface design, beginners must master

at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)

2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)

rebuild file in check for

这是一本关于verilog编程语言的教程,对学习verilog语言有帮助-This is the one on the Verilog programming language tutorial, Verilog language learning has helped

这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)

说明：  combinatorial modules