我用过的verilog hdl写的SDRAM core源程序,经过测试应用

a manual for design implementation of fpga and ASIC using verilog

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )

ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码(ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code)

SD卡读写源代码.用Verilog编写.很不错.值得借鉴.特别对SD卡开发的人员!(SD card reader-writer source code. Prepared to use Verilog. Is pretty good. Be used for reference. In particular, the development of personnel SD card!)

是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.

this program get 20 point from user and draw functions.

16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)

使用VHDL语言实现对快速傅立叶变换算法的实现，并通过仿真验证其正确性。(Using VHDL language implementation for the realization of fast Fourier transform algorithm, and its correctness is validated by computer simulation.)

数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)

通信系统帧同步信号的设计与实现，巴克码识别器系统完整VHDL程序，本人课程设计，完全能正常运行，程序运行环境为Quartus II 7.2 (32-Bit)，win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流，共同学习！！