A simple sequential lights

说明：  8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

Altera官方FPGA电机控制的中文文档，很不错的参考资料(Altera Official FPGA Motor Control Chinese Document, Good Reference)

3 Digit BCD to 7 segment indicator decoder

层合板的刚度的计算和验算，包括拉伸刚度A、弯曲刚度D以及耦合刚度B。 首先要给定层合板的各个参数，具体有：层合板的层数N；各单层的弹性常数E1、E2、 、G12；各单层对应的厚度；各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)

半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `

用verilog语言编译的pci协议实现，而且有具体的电路图(Compiled with the verilog language pci protocol implementation, but also the specific circuit)

点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

VESA CVT视频参数计算器，输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)