8位相 加乘法器，具有高速，占用资源较少的优点

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)

在 FPGA，SPI、 I2C 等 ASI，串行接口的实现来武力作为需要实现外围设备之间的接口。这个项目给 VHDL 源代码实施 SPI 接口和他们有关的文件。

This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.

电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed

Xilinx Licenses 2018

二维DCT，FPGA实现JPEG压缩中的二维DCT(dct)

设计要求1） 每帧数据供 10 位，其中 1位启动， 8位数据， 1位 停止。2） 波特率为： 9600 。3） 收发误码率

FFT VHDL code

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

北大verilog课件，数字集成电路设计入门，从HDL到版图-North Verilog courseware, digital IC design entry, from HDL to the map