采用VHDL英特尔8085微处理器的设计

Arty Z7 20 HDMI output

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

GF_2_m_域乘法器的快速设计及FPGA实现，对于rs编翼码的理解和设计有帮助-Domain multiplier GF_2_m_ rapid design and FPGA realization for rs wing made the understanding of code and design has helped

基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART )

计时范围为59.99秒；有计时开始和停止计时控制，复位控制可以对所有计时进行异步复位；计时结果由四位七段数码管显示。

verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table

Verilog for SPI Core source code

VHDL实现快速傅立叶变换 -VHDL implementation VHDL implementation of Fast Fourier Transform Fast Fourier Transform

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

基带数字信号通过成形滤波（选用升余弦滚降函数）然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)