SPI的核心源代码，verilog

说明：  uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given

利用xilinx开发板，使用嵌入式系统，编写的ps2键盘和利用dds原理产生正弦波的程序(Using xilinx development board, the use of embedded systems, the preparation of the ps2 keyboard and use the procedures dds elements of the sine wave)

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL

数字跑表 该跑表具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s 按钮设置防抖-Digital stopwatch in the stopwatch with start, reset, suspend, suspended after the time and other functions can show the seconds counting time accurate to the second place after the decimal point, that can show**.** s Anti-Shake button settings

用verilog写的很好的cpu core-using Verilog write a good cpu core

使用VERILOG开发时钟同步算法，能够从数据信号中提取时钟信息，(Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,)

vhdl表示与综合，原书第二版，中文版，比较全，用超星打开-vhdl

台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)

32-bit shifter, shifter, 32-bit.Very goog as a study file.