SPI的核心源代码，verilog

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

verilog code for bus controller

直接序列扩频系统的收发系统，可以进行参数配置(this is a Verilog program )

VHDL语言写的频率计的程序，内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

说明：  VGA图像显示，可实现图片和实现移动功能(VGA image display, enabling images and moving functions to achieve)

EEPROM 的verilog仿真模型（cat24cxx系列）(verilog simulition Model of EEPROM,include cat24cxx)

sourceinsight的verilog插件-The Verilog sourceinsight plug-ins

FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)

基于VHDL语言的并串转换程序，有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output