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一款verilog设计的SRAM控制器svtb_ahb_sram
一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
- 2020-06-30 13:40:02下载
- 积分:1
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VHDL language design stopwatch, timer function of the realization, the realizati...
VHDL语言设计的秒表,实现计时功能,实现报时功能,并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
- 2022-09-16 02:55:02下载
- 积分:1
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LED7s
七段LED数码管显示译码器设计,将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)
- 2021-04-23 23:28:47下载
- 积分:1
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SinglePeriodCPU
说明: verilog语言书写,单周期CPU源码(single period CPU)
- 2020-11-25 11:59:32下载
- 积分:1
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FPGA design of the guiding principles, it is classic! Want to give everyone easy
FPGA设计的指导原则,很经典的!希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy
- 2023-03-11 18:40:04下载
- 积分:1
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NRZ_2_Manchester_Moore
this example exchanges the NRZ code to the MANCHESTER code with moore output
- 2010-01-29 18:46:08下载
- 积分:1
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tb_axi4
介绍如何使用vivado来调用和封装IP核,测试AXI4总线的三种功能协议。(It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.)
- 2020-07-03 08:40:01下载
- 积分:1
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EDA
EDA技术及其应用《序列信号发生器的设计》,包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)
- 2012-10-29 18:30:40下载
- 积分:1
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ep2c5 实现 段寄存器,实验一
verilog语言,quartus 2 仿真
ep2c5 实现 段寄存器,实验一
verilog语言,quartus 2 仿真-Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation
- 2022-03-19 07:48:20下载
- 积分:1
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vivado 从此开始配套资料
vivado入门使用介绍,初学者入门学习(vivado Instructional pdf)
- 2020-07-04 18:00:01下载
- 积分:1