GF_2_m_域乘法器的快速设计及FPGA实现，对于rs编翼码的理解和设计有帮助...

一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)

VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.

七段LED数码管显示译码器设计，将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)

说明：  verilog语言书写，单周期CPU源码(single period CPU)

FPGA设计的指导原则，很经典的！希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy

this example exchanges the NRZ code to the MANCHESTER code with moore output

介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。(It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.)

EDA技术及其应用《序列信号发生器的设计》，包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)

ep2c5 实现 段寄存器,实验一 verilog语言，quartus 2 仿真-Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation

vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)