GF_2_m_域乘法器的快速设计及FPGA实现，对于rs编翼码的理解和设计有帮助...

flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定，激磁方式设定和定位角度的换算等工作，后一个模块用于对换算后的角度量编码输出。-This procedure to design an FPGA-based 4-phase stepper motor positioning control system. Direction set by the stepper motor circuit module, stepper motor stepper movement and positioning control module and the code output modules. The first two modules complete the motor rotation direction setting, exciting way of setting the angle and positioning of the conversion work, after a module for the point of view of the volume of converted output encoding.

利用c控制adc，主要是控制字写入，状态控制。-C control the use of adc, is mainly controlled write, the state of control.

说明：  基于sv的uvm平台搭建实战，对于验证方法学来说，分层的测试平台是一个关键的概念。虽然分层似乎会使测试平台变得更复杂，但它能够把代码分而治之，有助于减轻工作负担，而且重复利用效率提升。验证平台可以类似分为五个层次：信号层、命令层、功能层、场景层和测试层。(Construction of UVM platform based on SV)

mealy fsm å’Œmoore fsm-mealy Fsm and moore Fsm

verilog code for 8 bit alu

一个高级培训班的内部资料,非常宝贵,读者可以掌握FPGA的基本思路-A high-level training of internal information, are very valuable, readers can grasp the basic ideas FPGA

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)