用VHDL语言编写一计时范围为59.99秒的跑表

实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

说明：  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach

这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)

Programmable IIR Filter written in Verilog and its respective modules.

王金明的一些学习VHDL的子-Wang Jinming study of some subset of VHDL

说明：  简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

1553B总线BC端的编程例子，做通了对于一个RT的测试。对于其他的RT测试和程序的例子原理相同。(The BC end of the 1553B bus programming examples)

简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)