使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。

altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.

说明：  led学习控制l44444444444444(led verilog led ccccccc)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must

说明：  this code works with spi and uart interfaces.

ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL

VHDL与源代码包-and VHDL source code

这个是DE2上的SDRAM 四个端口的驱动代码，相当实用！(This is a four-port SDRAM on a DE2 driver code, very useful!)

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog