一路24位计数器,cpu可直接读写计数器的计数值.

采用Xilinx公司的Spartan6 FPGA设计PCI Express的详细参考资料(Xilinx' s PCI Express, Spartan6 FPGA design, detailed reference information)

Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. -Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.

a power point presentation presenting how to impliment EMF and GMF with DDS

Convolutional neural network code for fpga

基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)

DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under

sdram controller vhdl

WM8731芯片的音效处理verilog代码， WM8731芯片是音频ADCDAC芯片(WM8731 audio processing chip verilog code, WM8731 chip audio ADC DAC chip)

Interfacing RTC with spartan 3

verilog程序设计教程，适合初学者。-verilog programming tutorial for beginners.