The full version of the multiplier. I believe there is not a small improvement f...

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

工程实用观点，简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)

人的移动的跟踪，VERILOG实现，能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)

DS18B20温度传感器，用verilog语言实现(DS18B20 temperature sensor, with the verilog language)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

MVB架构流程图。MVB开发用，大连海天资料(MVB development, Dalian Haitian data)

一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加(A 32-bit floating-point adder can be both within the IEEE 754 format to add value)

xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)

--##############################################################################