JOP字节码获取的源码，很重要，具体FPGA中实现

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)

它是一个基于verilog的数字时钟，显示时-分-秒，它可以手动输入，并为时、分和秒分配3个开关第二，它数字时钟频率是实时设置的。我自己用逻辑开发的。。。

this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device

fpga学习中常用的缩略语-commonly used abbreviations

这本书介绍了数字应用的底层电路设计的理论及实验程序，非常有用，是一本很好的工具书。(This book describes the application of the underlying digital circuit design theory and experimental procedures, very useful, is a good tool.)

说明：  用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)

FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)

说明：  五阶CIC梳状积分滤波器，可以综合，非常有参考价值(Fifth-order CIC points comb filter, can be integrated and very useful)

嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl

多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )