是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。...

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)

thesis about design and implementation neural network using FPGA

train controler by verilog

Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)

this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal

说明：  VC707_MIG_DDR3.sim文件夹中是仿真的文件：testbench和DDR3模型参数 VC707_MIG_DDR3.srcs文件夹中是源文件，包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)

FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合-FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC

使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)

this come from alter ,you can look and find it on line about h263.