是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。...

　M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.

ahb to apb master and slave

输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2-a afdg jhg dfgh r fbnrfer

说明：  用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制(Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control)

modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

本实验教程选用Xilinx公司的产品X9572，与之配套的开发软件为ISE4.1i，可进行原理图的输入和VHDL硬件描述语言的输入，并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

硬件描述语言Verilog-Verilog hardware description language

用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)