FPGA development board to write the Verilog code: function is from the client co...

我的项目执行 filtrage 和抽取使用多相分解，在这种情况下，抽取因子被带到 5，所以筛选器由 5 集团过滤器和每个 oprates 在频率采样除以 5

说明：  CAN VHDL Code. Behavioral implementation of CAN bus interface.

GPU编程的经典之作,值得一读。 GPU运算效率比CPU高出一截，学习GPU编程会大有裨益(a book for GPU_Programming)

fpga 基于FPGA的mif文件创建与使用-fpga FPGA-based mif file creation and use of

一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)

binary comparator with register

pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)