基于FPGA的ramtest

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

锁相环是通信领域最基本的元件，同时在FPGA上也有广泛的应用，本代码是锁相环PLL的Verilog HDL代码，简单易读，能够实现PLL基本的锁相、分频等功能

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.

说明：  秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

说明：  FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)

Eliminate the program of key bounce

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)