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game
反应速度测试小游戏,最小外设cpld游戏,带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)
- 2010-05-14 18:42:57下载
- 积分:1
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RS
说明: 通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2013-07-18 16:09:22下载
- 积分:1
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锁相环Verilog代码
锁相环是通信领域最基本的元件,同时在FPGA上也有广泛的应用,本代码是锁相环PLL的Verilog HDL代码,简单易读,能够实现PLL基本的锁相、分频等功能
- 2022-01-26 00:06:30下载
- 积分:1
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4BITMUIT
利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)
- 2013-09-05 10:06:52下载
- 积分:1
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rd1020
Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design
due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola
MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.
- 2010-07-30 16:51:31下载
- 积分:1
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20181060261-李康_3
说明: 秒表的实现,有暂停清零功能,Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分:1
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sync-and-asyn_FIFO_verilog
同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
- 2021-03-07 14:19:29下载
- 积分:1
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Fast_median_filter
说明: FPGA数字图像处理实现均值滤波,并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分:1
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list_ch06_02_debounce
Eliminate the program of key bounce
- 2012-12-23 00:22:42下载
- 积分:1
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shift_split_data
关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)
- 2006-07-04 09:40:55下载
- 积分:1