1024乘法器

Parallel to Serial converter Module

APB是专为低带宽控制访问，就系统的外围设备例如寄存器接口。这种总线具有一个地址和数据相类似的AHB，但大大减少，低复杂度的信号列表中（例如，没有脉冲串）。它支持32位和66 MHz的信号。 APB主机和从机

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)

verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use )

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

说明：  用verilog状态机实现简单的自动售货机(Using Verilog state machine to realize simple vending machine)

串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)

RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code，　implement RS（204,188) )

把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)