DE2_70_D5M_LTM

Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

说明：  关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试(on an eight processors, and source code, VHDL design, the test)

e200 riscv open code user guide

按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)

一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)

这是OFDM调制matlab的程序，中间详细描述了调制的过程，希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)

说明：  microsemi的Libero IDE 软件内部IP核详解(Microsemi's Libero IDE software internal IP kernel details)

module LDPC (clk,reset,             data_in, data_in_en,             velocity, /*输入信号码率选择*/             data_out, data_out_en,             indication /*输出信号，第一个127要删除前5成7488，指示第一个127*/                );input   clk,reset;input   data_in,data_in_en;input[1:0]  velocity; //码率选择信号output[126:0]   data_out;output  data_out_en;output  indication;

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)