DE2_70_D5M_LTM

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

说明：  用verilog状态机实现简单的自动售货机(Using Verilog state machine to realize simple vending machine)

说明：  中科院FPGA的课件！纯英文，比较简单，适合刚刚接触FPGA的小白！(Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!)

针对AD9826驱动设计的Verilog代码，主要是配置ccd采样的设计(The Verilog code is designed for AD9826, to configuration ccd sampling )

这是完整的verilog控制ds18b20的程序，已在板子上运行了很长时间，很稳定，200M以下时钟皆可稳定运行（我是按照200M来设计的），上传的文件格式为.dat（在此不说明原因），下载后修改后缀名为.v即可使用，我也是为了积分才上传的，绝对可信，

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

说明：  用FPGA进行等精度频率和相位差测量的程序，本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)

128 位 aesverilog 代码 对于很多核心处理器阵列平行 aes 引擎