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Coding Files
Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
- 2017-12-13 23:58:23下载
- 积分:1
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seven-voting
用verilog 语言实现七人投票表决器(verilog seven voting)
- 2020-09-24 10:57:48下载
- 积分:1
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sobel
这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合和仿真,并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测,同时还可以实现其它的图像模块化处理算法,例如高斯滤波,平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)
- 2020-07-09 21:08:55下载
- 积分:1
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Verilog
基于FPGA的16QAM调制解调设计,以及仿真实现(Design of 16QAM Modulation and Demodulation Based on FPGA)
- 2021-02-19 16:29:44下载
- 积分:1
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shift_split_data
关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)
- 2006-07-04 09:40:55下载
- 积分:1
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pj_gtx
说明: 利用高速口GTX进行快速的数据传输,包括接受和发送模块,用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)
- 2019-03-25 21:40:10下载
- 积分:1
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Uart_Analysis
rs422通信,此模块实现通信功能,使用Verilog语言(RS422 communication program, Verilog language, this module implements 422 communication function.)
- 2021-03-23 16:29:15下载
- 积分:1
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Verilog数控分频器的设计
分析参考代码中的各语句功能、设计原理、逻辑功能,根据图1的波形提示,编写相应的Testbench文件代码,并用Modelsim进行仿真(仿真可以跳过时钟分频到100hz进程)。
在此基础上进行硬件验证。实验方法为:将clk接20Mhz时钟信号,rst_n接核心板开关S1,fout接发光二极管SD0,预置值d从DKA0-DKA7输入,改变d的输入,从发光二极管SD0判断输出信号的频率。
- 2022-11-07 09:25:04下载
- 积分:1
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DFT
说明: DFT FPGA实现,simulink到vivado(DFT FPAG implement base on simulink and HLS)
- 2020-09-22 18:08:58下载
- 积分:1
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Walsh
说明: 利用ISE编写的产生WALSH码的verilog程序,简单易懂,稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码。。(Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16,32,64-bit code WALSH. .)
- 2010-04-20 09:55:10下载
- 积分:1