基于Verilog的IIC协议的实现

这是一个关于 VLSI 设计项目。主题是设计用于CORDIC （为 CO纵坐标 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

设计制作一个检测4*4矩阵键盘的按键编码的实验，把实际按键的键值的八位编码先转换成从0000—1111的编码，再译成数码管能识别的八位编码，在数码管动态显示时，4*4矩阵键盘的第一行对应00—03，第二行对应04—07，第三行08—11，第四行对应12—15。(Design a 4* 4 matrix keyboard key coding experiments to detect the key the actual key octet coded first convert from 0000-1111 encoding, and then translated into digital tube to identify the eight coding, digital tube dynamic display, the first line of the 4* 4 matrix keyboard corresponding to 00-03, the second line corresponds to 04-07, the third line of 08-11, the fourth line corresponds to 12-15.)

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)

AD7685芯片采集程序，可以自行设置采样率，经检验可用。(The AD7685 chip collection procedures, available.)

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)

用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码(Ethernet controller based on Verilog, can be used directly, all verilog files)