GPS 码 nco 码跟踪环累加模块设计

这个项目给出FIFO.Since buscan连接于不同的数据速率操作的设备，先入先出（FIFO）存储器的需要，以适应useof在I2C在I2C。 WithFIFO存储器，一快速的设备可以与通过theFIFO缓冲非常慢的设备进行通信。在另一方面，如果快速和低设备连接togetherwithout缓冲器时，快速的设备将必须等待低设备finishtransfer或接收的数据;但通过使用缓冲液中，在快速设备将bekept忙于处理信息到缓冲区。这是writteninto内存中的数据首先是第一个TOBE读出。

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

i2c master ip for altera nios, add in qsys

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)

资源描述 本设计中可以实现测量周期，测量方波的占空比，被测范围1Hz-100MHz。相对误差小于0.001%. 可以测方波、正弦波等波型。同时还有上下左右按键控制显示

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)

Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)

OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)