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DDS_signal_genarator
这是一个利用verilog语言编写的信号发生器的例子,值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)
- 2013-12-23 10:12:52下载
- 积分:1
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Receiver
该程序是整个OFDM接收机的程序,希望对做这方面的朋友用些帮助,也希望朋友们和我一起探讨OFDM收发信机。(The program is the whole OFDM receiver process, hope to do in this area with some friends to help and also hope that friends and I explore OFDM transceiver.)
- 2010-01-03 13:44:38下载
- 积分:1
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Elevator designed to control the lift design 6 original VHDL language
电梯的设计・用来控制6层的电梯设计原来・VHDL语言-Elevator designed to control the lift design 6 original VHDL language
- 2022-02-06 15:18:21下载
- 积分:1
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forug_2016.03
说明: formality2016 userguide
- 2019-10-29 14:59:40下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including...
USB 1.1 PHY的代码,systemc语言 USB 1.1 PHY的代码,systemc语言,包括基于systemc语言的testbench ,和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
- 2022-04-12 00:51:05下载
- 积分:1
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Digital_filterin_code
MATLAB辅助设计数字滤波器源代码,QUATUS II 实现!(MATLAB-aided design of digital filter source code, QUATUS II implementation!)
- 2009-03-31 13:19:42下载
- 积分:1
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多人抢答器 源代码 实用 课程设计 用用VHDL语言
多人抢答器 源代码 实用 课程设计 用用VHDL语言-The source code for more than Responder practical courses designed for use with the VHDL language
- 2022-04-21 18:03:26下载
- 积分:1
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通过VHDL语言的例子,乒乓球运动的FPGA原型样机(2章)是
应用背景FPGA原型的VHDL例子提供一系列清晰,易于遵循的快速代码开发模板;大量的实际例子来说明和强化的概念和设计技术;现实可实施的项目和测试在Xilinx原型板;深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-08-13 14:19:44下载
- 积分:1
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LDPC_Encoder
说明: verilog 编写的ldpc编码,含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分:1