vhdl实现8255,可重用，ALATEK公司提供验证，用说明文档

FSK编码器和译码器,有需要的朋友可以看看！(FSK encoder and decoder, there is a need friends can see!)

基于verilog convolutional coding 的卷积编码(verilog convolutional coding )

上海交通大学电子信息与电气工程学院VHDL经典教程-Shanghai Jiaotong University Electronic Information and Electrical Engineering, Institute of Classical VHDL Tutorial

关于MPEG压缩的程序，里面有较多的源代码和完整的说明是用MICROBLAZE完成的。(On the MPEG compression process, there are more source code and complete description is completed with MicroBlaze.)

用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.

codes for zynq devices

fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University

24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.

此程序是Verilog HDL语言读写RAM的程序希望大家有用(This is Verilog HDL Promang)

说明：  matlab code for JTAG cable checking