自己编写的只读存储器ROM16*8的试试很好用的

Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)

数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

下面是各种文件，有 vhdl 代码和进位保留加法器的验证平台，进行超前进位加法器，等等。综合和代码已经模拟了。 给出的所有加法器是 16 位加法器，并实施新思科技。

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

这是altera公司的DE2-35开发板下的一个液晶显示屏源程序代码工程，液晶显示屏是友晶公司的，包括液晶显示屏的驱动以及显示等模块有需要的人，可以下载 (Altera DE2-35 development board of the company, a liquid crystal display source code engineering, LCD display the Terasic, including LCD driver module and display needs, you can download)

Building the CPU datapath

this is a vhdl program...

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)