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PWM
基于FPGA的PWM控制器设计,包含ADC0820模块,按键扫描,PID,PWM控制器等模块,VHDL语言完成,已仿真通过(PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation)
- 2016-05-01 15:05:58下载
- 积分:1
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traffic_lights
交通灯控制器控制红(r)、绿(g)、黄(y)三种不同颜色的交通灯,这三种不同颜色灯的亮、灭分别由三个定时器(timer1、timer2、timer3)控制;
当某个定时器工作时,它所控制的交通灯亮,直到设定的定时时间到(该定时器状态由’0’变’1’),交通灯跳转到另一种状态;
clk是脉冲控制端(图中未标出);reset是异步复位端,复位状态为红色交通灯亮;
输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。
( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights output terminal r, g, y represent the three colors of traffic lights bright, the off state.)
- 2020-12-19 15:09:10下载
- 积分:1
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FPGA源代码
FPGA源代码公布,包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序,LED静态显示ADC0809 VHDL控制程序,DAC0832 接口电路程序
- 2022-04-26 16:23:11下载
- 积分:1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
- 2022-08-23 17:16:15下载
- 积分:1
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qam_64
64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核(64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS)
- 2021-03-02 23:29:33下载
- 积分:1
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基于FPGA的快速傅立叶变换实现,适合fpga工程技术人员参考设计...
基于FPGA的快速傅立叶变换实现,适合fpga工程技术人员参考设计-FPGA-based Fast Fourier Transform for fpga reference design engineers
- 2022-12-10 15:50:11下载
- 积分:1
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msk_mod_demod
该程序实现最小频移键控信号的调制解调,经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)
- 2013-10-14 23:02:39下载
- 积分:1
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4:2优先编码器的VHDL代码
4:2优先编码设计中的VHDL来为每个输入分配优先级。在CMOS布局1复用器:还设计了4个
- 2022-02-11 13:12:33下载
- 积分:1
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基于altera系列芯片lvds接口的fpga设计 verilog源码
基于altera系列芯片lvds接口的fpga设计 verilog源码-Series altera-based chip interface lvds source fpga design verilog
- 2023-08-31 17:40:04下载
- 积分:1
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vga_graph_st
该程序用vhdl编写的vga显示的小游戏,到时屏幕上会显示一个小球,一根棒子,一面墙,棒子可以通过按键控制来移动。而小球在不停的运动,遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)
- 2013-05-18 21:01:23下载
- 积分:1