Srikanth Vijayaraghavan

project proposal of verilog language that is gud for beginners

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

DE2将连接到LCD布局上，为Terasic off技术公司附上系统代码

DDS分频实现，全部代码的完整过程，包括截图等(DDS divider to achieve the complete process of all the code)

说明：  实现数字频率合成实验，加载数据ram,形成波形(The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform)

说明：  基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)

UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列 UG C program，homework，student，study，first，hole，complex，many( UG C program，homework，student，study，first，hole，complex，many)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)