登录
首页 » VHDL » Srikanth Vijayaraghavan

Srikanth Vijayaraghavan

于 2022-05-29 发布 文件大小:10.12 MB
0 183
下载积分: 2 下载次数: 1

代码说明:

Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 可综合的Verilog语法和语义,从大学教师cambri…
    《可综合的Verilog语法》国外著名大学老师编写,对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
    2022-03-31 07:34:29下载
    积分:1
  • 用VHDL实现十六位移位乘法器 才有移位相加法来实现
    用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
    2022-04-17 17:23:11下载
    积分:1
  • dds
    基于DDS的信号源设计(包括三角波、正弦波、方波)(Design of signal source based on DDS)
    2018-01-01 18:06:51下载
    积分:1
  • MPU6050
    FPGA 控制MPU6050陀螺仪传感器,通过串口把数据打印出来(FPGA controls the MPU6050 gyroscope sensor and prints out the data through the serial port)
    2018-02-10 16:45:24下载
    积分:1
  • Farrow
    matlab代码,利用Farrow结构设计分数延时滤波器,滤波器阶数和个数可分别进行设置,利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
    2021-03-28 22:29:11下载
    积分:1
  • 试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左,然后从左到右逐次点亮,全灭全亮;第二种花样为彩灯两边同时亮一个逐次向...
    试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左,然后从左到右逐次点亮,全灭全亮;第二种花样为彩灯两边同时亮一个逐次向中间移动再散开;第三种花样为彩灯两边同时亮两个逐次向中间移动再散开;第四种花样为彩灯两边同时亮三个,然后四亮四灭,四灭四亮,最后一灭一亮。四个花样自动变换,重复以上过程。输入时钟频率为500Hz,灯亮的时间在1―4秒之间,可以自由控制。电路中以“1”代表灯亮,以“0”代表灯灭。-Lantern try to design a controller to control 8 lights. The controller has four kinds of lanterns automatically switch the pattern. The first lantern pattern for right-to-left, and then lit from left to right each time, the whole body light second pattern for a lantern light at the same time on both sides of successive spread to the middle of moving again third pattern for lantern light at the same time on both sides to the middle of two successive re-dispersed mobile fourth pattern for the lantern light at the same time on both sides of the three, then four out four bright, four out four-liang, the last light out. Automatically transform the four patterns, repeat the process above. Input clock frequency of 500Hz, the time for lights between 1-4 seconds, they can con
    2022-08-19 21:54:46下载
    积分:1
  • FPGA_Cordic_Atan_A
    串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)
    2014-10-13 20:55:52下载
    积分:1
  • 基于nios ii 驱动altera de1开发板上的lcd和ps2鼠标模块工程
    基于nios ii 驱动altera de1开发板上的lcd和ps2鼠标模块工程-based on the nios ii drive the lcd and ps2 module of altera de1 develop board
    2022-03-12 01:14:50下载
    积分:1
  • CycloneIIFPGA chip
    基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序,用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation
    2023-05-02 05:35:04下载
    积分:1
  • 使用vriloge硬件描述语言设计数字频率计,其对于高频测量精确,可测范围0―99999999HZ,在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求...
    使用vriloge硬件描述语言设计数字频率计,其对于高频测量精确,可测范围0―99999999HZ,在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求-The use of hardware description language design vriloge digital frequency meter, and its high-frequency measurement for accurate, range 0-99999999HZ, in MAX+ PLUSII run me through and run the experiment to meet the requirement through
    2022-01-25 18:01:01下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载