4x4键盘模块。这个文件包括普通的键盘设计方案说明和相关的原程序。...

EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)

内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持： 1、 对目标PCI_T进行配置； 2、 对目标进行单周期读写； 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of

该书介绍了英特尔的80x86CPU和一些串行通信芯片，以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)

用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

8 bit cpu vhdl design code not tested

vhdl编写的4X4键盘扫描程序，可以有效的消除抖动，并且提供蜂鸣器输出。(VHDL prepared 4X4 keyboard scanner, you can effectively eliminate jitter and provide buzzer output.)

利用EGO1数模混合口袋实验平台上的蓝牙模块与板卡进行无线通信。使用支持蓝牙 4.0 的手机与板卡上的蓝牙模块建立连接，并且通过手机 APP 发送命令，控制 FPGA 板卡上的硬件外设。(The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.)

说明：  lvds_rx IP核硬件设计代码，使用时注意LVSD_RX模块的延时参数的设置，3.5倍时钟相位的设置(Lvds IP core hardware design code, when using the attention LVSD module delay parameter settings, 3.5 times the clock phase settings)

fir filter 程序 老师上课留的作业，在这里跟大家分享一下，希望能有所帮助(fir filter procedures teacher in the class to stay the operation here to share with you, hope can be helped)