4x4键盘模块。这个文件包括普通的键盘设计方案说明和相关的原程序。...

一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using

VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA

不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！()

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.-Using Verilog HDL language hardware design, the realization of the basic public telephone billing function, design integrity.

基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)

能够绘制数字电路的时序图，是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)

这是一个EOS项目中的GFP成帧结构，能够容错，可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)

DDS in our camera design

VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)