单片机与FPGA串行通信的源代码，非常实用哦

parllel toserial out test bench

用verilog状态机实现的自动售货机，是一次课程作业，参考了网上的例子进行了修改(Automatic vending machine implemented with Verilog state machine)

用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the

流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)

74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)

ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.

基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示(TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions)

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )