I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code

code for booths multiplier

SPI Verilog code with programmable clock

Service Manual LG TV LCD DISPLAY models 2011

LDPC COded OFDM System

说明：  试用Verilog HDL语言，设计十进制计数器，将计数过程用一个数码管进行显示（0～9）。要求首先使用Modelsim软件进行功能仿真，然后使用Quartus软件综合，并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

Coding Styles for if Statements and case Statements

Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)

FPGA的SRAM存储器的控制程序，包括时序测试-FPGA

XAPP585 serdes_1_to_7 and serdes_7_to_1 data