8位深，9位宽FIFO VHDL源码设计，如需改进可在此基础上扩展

说明：  fpga设计常用资料大全，包含常用的FPGA程序资料，对FPGA学习者有很大的帮助。(Encyclopedia of common information fpga design, FPGA that contains commonly used procedures for information on the FPGA is very useful to learners.)

DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)

该计数器可以实现从0到1000的技术，程序简练执行效率高(counter1000)

本实例用于SDRAM完成读写功能: 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。(The examples for SDRAM read and write functions.)

使用信号功率计算，检测信号是否到达。从而控制后续模块，以减小系统功耗。(Signal power calculation, the detection signal to reach. To control follow-up modules to reduce system power consumption.)

找到这本书的完整版了。呵呵，贴出来和大家共享。这是本好书，我买了一本作为Verilog的参考书。这本书语法部分集中，便于查阅，此外讲了很多实用的设计思想。最重要的是本书薄，可以完整看完。强烈推荐。 （如果只是查阅，电子版就可以，如要完整学习，建议还是买纸质版的）(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))

本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of

vhdl code for carry lookahead addder

Xilinx PicoBlaze application developed in ISE10.1.3.

使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public