-
fpga_debounce_filter
fpga debounce filter code in vhdl
- 2009-10-02 18:48:22下载
- 积分:1
-
uart
9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)
- 2011-08-22 17:57:52下载
- 积分:1
-
利用FPGA串口通信向上位机发送数据
利用FPGA串口通信向上位机发送数据,使用RS232通信协议,向上位机发送8位数据,其中8八个数据位包括4个信息位,经过7-4汉明编码变为7个信息位,而最低位补0,发送的8位数据为2个16进制数,其2个16进制数通过数码管显示。
- 2022-03-15 00:32:55下载
- 积分:1
-
y210
三八译码器,四位加法器,EDA实验,用verilog编写(EDA experiment with verilog language)
- 2017-10-30 20:14:30下载
- 积分:1
-
modulationshaped
基带数字信号通过成形滤波(选用升余弦滚降函数)然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)
- 2007-10-31 15:27:18下载
- 积分:1
-
adda
说明: 基于FPGA 黑金ALINX 515的 ADDA采样模块源码(需调试)(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)
- 2020-06-20 13:00:01下载
- 积分:1
-
AHB-answers
这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)
- 2020-10-21 12:17:24下载
- 积分:1
-
fault
fault minimization using genetic algorithm
- 2013-11-19 20:05:06下载
- 积分:1
-
VHDL language is designed to be simple to use the CPU, the focus of the design o...
用VHDL语言设计简单的CPU,重点设计微操作代码,然后设计CPU各组成模块,最后根据设计的微操作设计微指令,验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
- 2022-01-26 04:06:25下载
- 积分:1
-
用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.
用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.-write VHDL VGA core, is a very good subset of the core, has a lot of functions.
- 2022-01-26 04:58:14下载
- 积分:1