8位深，9位宽FIFO VHDL源码设计，如需改进可在此基础上扩展

VHDL实用教程（潘松）,非常经典讲解VHDL语言，包含基本语法及实例。-VHDL Practical Guide (Pan Song), is a classic on the VHDL language, including basic grammar and examples.

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 -I am learning more systematic series of practical VHDL source Giant

说明：  基于FPGA的OFDM同步，包含时钟模块、ROM读取模块、峰值检测模块、帧同步模块(OFDM synchronization based on FPGA includes clock module, Rom reading module, peak detection module and frame synchronization module)

使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

利用分频可以产生一系列脉冲，根据输入脉冲的不同决定你得到的一系列脉冲频率-The use of sub-band can produce a series of pulses, according to input pulse of different decisions you have a series of pulse frequency

AM modulated learning ladder

中科院VHDL学习资料，很好的东西，希望对大家有用-Chinese Academy of Sciences VHDL learning materials, a very good thing, everyone would like to be useful

用VHDL 语言驱动DM128*64LCD程序-Using VHDL language driver DM128* 64LCD procedures

一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference