用verilog hdl 硬件描述语言写的一个范例程序，led的，扩展性极强，欢迎大家下载使用。...

本设计是一个伪随机数发生器。此设计；

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

combinational circuits code in vhdl

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

在这个项目中我们使用 DE2 115 板上显示每次通过转移在左边按下某个键滚动你好。 这种架构使用管道和多路复用器

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

用fpga实现VGA16色真彩的图片显示,且在AX301实验板上已经调试过(VGA16 achieve true color with fpga pictures show, and in the AX301 has been tuned breadboard)

parllel toserial out test bench

H.265的FPGA实现！！使用Verilog语言开发。(H.265 FPGA implementation! Developed using Verilog language.)

8251的完整的功能的实现,可以进行编译,综合.-8251 complete function of the realization can be compiled and integrated.