用verilog hdl 硬件描述语言写的一个范例程序，led的，扩展性极强，欢迎大家下载使用。...

是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.

说明：  FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures

ALTERA FPGA CLPD

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

基于FPGA的OFDM的实现，Verilog语言。(OFDM based on FPGA,by Verilog)

友晶 altera DE2开发板中文用户手册，对DE2开发板的完整介绍。(DE2 development board Chinese user manual, a complete description of the DE2 board.)

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.

分数阶Unscented卡尔曼滤波器研究.pdf(Fractional Unscented Kalman filter pdf)