电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

This is an UART real time clock

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.

vhdl 语言实例，包括各种逻辑门的构造。-Examples of VHDL language, including a variety of logic gate structure.

this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.

FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)

VHDL基本运算，采用8位为乘法器，将两个8位字符串的值输入相乘后

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

说明：  俄罗斯方块游戏，采用Verilog编写，整个工程文件，TFT/VGA显示(Tetris game, written by Verilog, the whole project file, TFT / VGA display)

8051核的vhdl原代码。-8051 core VHDL source code.