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breath
利用verilog写的PWM 程序,来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)
- 2020-06-17 04:40:01下载
- 积分:1
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VHDL语言串口接收数据
VHDL语言,实现穿行数据接收的功能,将异步串口的数据转换为八位数据存储。
- 2022-03-24 16:10:35下载
- 积分:1
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HB1
半带滤波器,用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分:1
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yuandaima
以GPS为时间基准,实现多传感器器数据同步采集,整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分:1
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*** ***OC_I2C_Master使用说明*** *****
使用步骤:1.将OC_I2C_Master文件夹拷贝到安装盘alterakits...
*** ***OC_I2C_Master使用说明*** *****
使用步骤:1.将OC_I2C_Master文件夹拷贝到安装盘alterakits
ios2components目录下。
之后重新打开SOPC Builder,在可用元件列表的DeviceSOPC组中将出现OC_I2C_Master
元件,即可像其它Altera外设元件一样添加和使用。
2.hdl文件夹中包含有描述i2c逻辑的硬件描述文件,不能删除。
3.HAL文件夹包含硬件抽象层所需的文件(即驱动),不能删除。
4.inc文件夹包含有定义底层硬件的C语言头文件,不能删除.
5.I2C_doc文件夹下有关于该元件的开发文档。-********* OC_I2C_Master use*********** use these steps: 1. OC_I2C_Master folder will be copied to the installation disk alterakits ios2components directory. Re-open after the SOPC Builder, a list of available devices will appear DeviceSOPC Group OC_I2C_Master components, can be similar to other peripheral devices like Altera add and use. 2.hdl folder contains logical description i2c hardware description files, can not be deleted. 3.HAL folder contains the necessary hardware abstraction layer file (ie drivers), can not be deleted. 4.inc folder contains the definition of the underlying hardware C language header files, should not delete. 5.I2C_doc folder on the developmen
- 2022-04-07 04:49:42下载
- 积分:1
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82 VHDL, verilog test case, involving a variety of grammatical rules. which is...
包括VHDL、verilog在内的各种设计实例,是学习硬件描述语言的帮手。共有82个实验例子,涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
- 2023-06-06 10:15:04下载
- 积分:1
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这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核,文档齐全...
这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核,文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
- 2022-02-21 05:05:05下载
- 积分:1
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8.8-URAT-VHDL
URAT VHDL程序与仿真 URAT the VHDL program and Simulation
(URAT the VHDL program and Simulation
)
- 2012-04-09 20:53:45下载
- 积分:1
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FPGA Verilog HDL模拟IIC通讯接口
FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface
- 2023-04-25 13:55:03下载
- 积分:1
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ces_svtb_2011.12
synopse sv培训lab,是学习systemverilog非常好的资料,放心下载。(synopsis sv training lab)
- 2021-04-19 11:18:51下载
- 积分:1