初学ＶＨＤＬ有用的，了解后对复杂设计有很大帮助．

user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

ADS是安捷伦科技公司的EDA软件这个库的等效电路数据使用ADS2011，后来只。（请参阅ADS2009U1有关图书馆的信息和更早版本）

这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)

模拟示波器的现实程序，有x，y和光标。采用AD5440输出，现实效果很好。（示波器x-y方式）(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

vhdl语言例程集锦.pdf，全部的例子，看你会不会偷了-VHDL language routines Collection. pdf, all the examples, you will not see stealing

ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)

说明：  AD6 中进行FPGA设计与仿真，很不错的资料哦(FPGA design and Simulation in AD6, very good data)