在 2 线液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD HIỂN THỊ 2 HÀNG) CODE_VHDL_INITIALIZING

说明：  使用FPGA实现RGB图像转灰度图像的算法，下载入自己的电路板可直接将摄像头拍摄到的图像实时转换成灰度图像(FPGA is used to realize the algorithm of transforming RGB image into gray image. The image captured by the camera can be converted into gray image in real time by downloading it into its own circuit board)

全加器的VHDL程序实现及仿真-full adder VHDL simulation program and

RS(255,223)编码器程序 从一本书上看到的，很不错的(RS(255,223) encode , very good good good )

利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter

1．初始状态为4个方向的红灯全亮，时间1秒。 2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。 3．东、西方向黄灯闪烁，南、北方向红灯亮。时间2秒。 4．东、西方向红灯亮，南、北方向绿灯亮。南、北方向通车，时间15秒。 5．东、西方向红灯亮，南、北方向黄灯闪烁。时间2秒。 6．返回2，继续运行。 -1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.

Demo program for use UART STM8S

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)